Conventionally, as an interface circuit interconnecting circuits operated in different power supply voltages, various types of level shift circuits are used. As one of the related art references, a circuitry corresponding to such a circuit illustrated in FIG. 6 of Patent Document 1 (Japanese Patent No. 3176339) is shown in FIG. 13. The input signals or ‘IN’ and ‘INB’ of this circuit are digital signals whose high and low levels are both within the voltage range of 0V or higher. The output signals ‘out’ and ‘out B’ take the positive and negative voltage ranges. With reference to FIG. 13, the state and the node voltage of the respective p-type MOS transistors M11 and M12 coupled to the input nodes ‘in’ and ‘in B’ when they are turned on and off are shown in FIG. 14. The signals whose voltages V1 and 0 applied to the input nodes ‘in’ and ‘in B’ are converted into signals whose voltages are V1 and V2 or the positive and negative voltage levels at the output terminals ‘out’ and ‘out B’. Further, in this state, at least one of the vertically stacked MOS transistors is in the off-state, so that the flow-through current does not flow. In addition, the voltage applied between arbitrary two terminals among the gates, sources, drains of the respective MOS transistors is less than or equal to V1 or less than or equal to |V2|. That is to say, in spite of the fact that the output voltage amplitude of this circuit is V1+|V2|, it can be comprised of MOS transistors whose maximum applicable voltage is more than or equal to V1 and |V2|. Further, this circuit transmits a DC signal, so that an output state according to an input signal can be obtained from the time of the power-on.
Moreover, in Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2008-199153), such a level shift circuit is disclosed as reducing the voltage between the source and the drain of a transistor and alleviating the high maximum applicable voltage property of such transistors.
[Patent Document 1]
Japanese Patent No. 3176339
[Patent Document 2]
Japanese Patent Kokai Publication No. P2008-199153A